Sixth International Workshop on FPGAs for Software Programmers (FSP 2019)

September 12, 2019, Barcelona, Spain co-located with International Conference on Field Programmable Logic and Applications (FPL)

Cite this publication as

Christian Hochberger (Hg.), Dirk Koch (Hg.), Markus Weinhardt (Hg.), Sixth International Workshop on FPGAs for Software Programmers (FSP 2019) (2019), VDE Verlag, Berlin, ISBN: 9783800750467

21
accesses

Descripción / Abstract

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers.Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists.With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken.

The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends.This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized targetplatforms.This will in particular put focus on the requirements of software developers and application engineers.In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware.Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development.In addition, the FSP Workshop shall facilitate collaboration of the different domains.

Topics of the FSP Workshop include, but are not limited to:
• High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
• Mapping approaches and tools for heterogeneous FPGAs
• Support of hard IP blocks such as embedded processors and memory interfaces
• Development environments for software engineers (automated tool flows, design frameworks and tools, tool interaction)
• FPGA virtualization (design for portability, resource sharing, hardware abstraction)
• Design automation technologies for multi-FPGA and heterogeneous systems
• Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility, reliability, or programmability
• Operating system services for FPGA resource management, reliability, security
• Target hardware design platforms (infrastructure, drivers, portable systems)
• Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
• Applications (e.g., embedded computing, signal processing, bio informatics, big data,database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
• Directions for collaborations (research proposals, networking, Horizon 2020)

Índice

  • Sixth International Workshop on FPGAs for Software Programmers (FSP 2019)
  • Titlepage
  • Imprint
  • Preface
  • FSP 2019 Co-Chairs
  • FSP 2019 Proceedings Co-Chairs
  • FSP 2019 Program Committee
  • Content
  • Keynotes
  • Addressing High-level Synthesis Challenges for Heterogenous Computing at the Edge
  • Architecture Virtualization as Prerequisite for Large-Scale FPGA Adoption In Software Communities
  • Session 1 „HLS Acceleration and Optimization“
  • Accelerating Human Activity Recognition Systems on FPGAs through a DSL approach
  • Accelerating Design Convergence of Automata Processing Designs with a Tiled Hierarchy
  • Impact of Off-Chip Memories on HLS-Generated Circuits
  • Session 2 „Heterogeneous Systems and Runtime Support“
  • libGalapagos: A Software Environment for Prototyping and Creating Heterogeneous FPGA and CPU Applications
  • Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI
  • ZUCL 2.0: Virtualised Memory and Communication for ZYNQ UltraScale+ FPGAs
  • Invited Talks and Tutorials
  • fpgaConvNet and f-CNNx: Towards addressing the challenges in ML application deployment
  • OpenCL design flows for Intel and Xilinx FPGAs: Using common design patterns and dealing with vendor-specific differences
  • Care of magical creatures – How to tame, train and feed your Alveo or Stratix FPGA card
  • Ihre Meinung zählt!

Títulos relacionados