Microprocessor Design Using Verilog HDL

Produktinformationen

ISBN: 9780963013354
Verlag: Elektor
Erscheinungstermin (elektronische Fassung): 2017-11-12
Seiten: 341
Paket: Programmierung [3175]

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Microprocessor Design Using Verilog HDL (2017), Elektor, Aachen, ISBN: 9780963013354

Inhaltsverzeichnis

  • Microprocessor Design using Verilog HDL
  • All rights reserved
  • Table of Contents
  • Preface
  • 1. Introduction
  • Goals of This Book
  • Target Audience
  • What to Expect
  • Typeface Conventions
  • 2. Verilog HDL
  • Overview
  • Data Types and Their Use
  • Bit Widths and Labeling
  • Logical Operations
  • Arithmetic Operations
  • Conditional Statements
  • Case Statements
  • Procedural Statements
  • Design Hierarchy
  • The Power of `define
  • Conditional Compilation
  • Aggregating Files With `include
  • 3. Verilog Coding Style
  • Importance of Coding Style
  • Files Versus Modules
  • Indentation
  • Naming Conventions
  • Inputs, Outputs and Variables
  • Comments and More Comments
  • Overall Design Organization
  • 4. Initial Design Work
  • Introduction
  • Instruction Set Architecture
  • External Bus Interface
  • Machine Cycle
  • 5. Microarchitecture
  • Introduction
  • Organizing the Design Spreadsheet
  • The Operation Worksheet
  • The Internal Code Worksheet
  • The Big Picture
  • Machine Cycle Details
  • The Next State Worksheet
  • When to Add a Worksheet
  • The Tran Type Worksheet
  • The Address Bus Worksheet
  • The Pre-address Worksheet
  • The Load PC Worksheet
  • The DinDout Worksheet
  • The ALU Op, ALU A and ALU B Worksheets
  • The Register Wr Worksheet
  • The S flag Worksheet
  • The Z flag Worksheet
  • The H flag Worksheet
  • The PV flag Worksheet
  • The N flag Worksheet
  • The C flag Worksheet
  • The T flag Worksheet
  • The Special Case Worksheet
  • 6. Writing the Verilog
  • Introduction
  • The defines.v file
  • The hierarchy.v file
  • The machine.v module
  • The extint.v module
  • The aluamux.v module
  • The alubmux.v module
  • The alu_math.v module
  • The alu_log.v module
  • The alu_shft.v module
  • The aluout.v module
  • The datapath.v module
  • The control.v module
  • The y80_top.v module
  • 7. Debug, Verification and Testing
  • Introduction
  • Debug Requirements
  • Verification Requirements
  • Testing Requirements
  • The Testbench
  • 8. It’s Finally Done. Now what?
  • Introduction
  • The Details
  • Enhancements
  • Index
  • Appendix
  • Figures
  • Listings
  • Tables
  • Resources/Bibliography

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